학력
-2014.02 KAIST, Electrical Engineering (Ph.D.)
-2010.02 KAIST, Electrical Engineering (M.S.)
-2008.02 Yonsei University, Electrical Engineering (B.S.)
주요 경력
- 2022.02 - Present Seoul National Univ. of Science and Technology (Assistant Professor)
- 2014.02 – 2022.01 SK Hynix (Senior Engineer)
주요논문 및 저서
- Surface-controlled Ultrathin (2 nm) Poly-Si Channel Junctionless FET towards 3D NAND Flash Memory Applications, Symposium on VLSI Technology, 2014
- Origin of transient Vth shift after erase and its impact on 2D/3D structure charge trap Flash memory cell operations, International Electron Devices Meeting (IEDM), 2012
- Dramatic Improvement of high-K Gate Dielectric Reliability by Replacing Metal Gate Electrode with Mono-Layer Graphene, Symposium on VLSI Technology, 2012
- Graphene Gate Electrode for MOS Structure Based Electronic Devices, Nano Lett., vol. 11, no.12, pp. 5383-5386, 2011
저널 논문
- A Review of Cell Operation Algorithm for 3D NAND Flash Memory, Applied Sciences, vol. 11, no. 21, pp. 10697, 2022
- Dependence of grain size on the performance of a polysilicon channel TFT for 3D NAND flash memory, J. Nanosci. & Nanotech., vol. 16, no. 5, pp. 5044-5048, 2015
- Improvement of the multi-level cell performance by a Soft Program Method in Flash Memory Devices, Solid State Electron., vol. 94, pp. 86-90, 2014
- Comparative Study of Chemically Synthesized and Exfoliated Multilayer MoS2 Field Effect Transistors, Appl. Phys. Lett., vol. 102, pp. 043116, 2013
- Improvement of Charge Retention in Flash Memory Devices by Very Light Doping of Lanthanum into an Aluminum-Oxide Blocking Layer, Appl. Phys. Express, vol. 5, pp. 081102-1~081102-3, 2012
- Determination of Work Function of Graphene under a Metal Electrode and Its Role in Contact Resistance, Nano Lett., vol.12, no.8, pp 3887-3892, 2012
- Graphene Gate Electrode for MOS Structure Based Electronic Devices, Nano Lett., vol. 11, no.12, pp. 5383-5386, 2011
- Lanthanum-Oxide-Doped Nitride Charge Trap Layer for a TANOS Memory Device, IEEE Trans. Electron Devices, vol. 58, no. 10, pp. 3314-3320, 2011
- Mechanism of Date Retention Improvement by High Temperature Annealing of Al2O3 Blocking Layer in Flash Memory Device", Jpn. J. Appl. Phys., vol. 50, no. 4, pp. 04DD07-1-04DD07-5, 2011
- Cubic-Structured HfLaO for the Blocking Layer of a Charge-Trap Type Flash Memory Device, Appl. Phys. Express, vol. 3, no. 20, pp. 091501-1-091501-3, 2010
- Improvement of Memory Performance by High Temperature Annealing of the Al2O3 Blocking Layer in a Charge-Trap Type Flash Memory Device, Appl. Phys. Lett., vol. 96, no. 22, pp. 222902-1-222902-3, 2010
- Structural and Compositional Dependence of Gadolinium-Aluminum Oxide for the Application of Charge-Trap-Type Non-Volatile Memory Devices, Appl. Phys. Lett., vol. 96, no. 5, pp. 052907-1-052907-3, 2010
◾ Reducing Interface Resistance in Semiconductor System Through the Integration of Graphene, ELECTRONICS, vol.13 No.21, 2024박종경
◾ Analysis of Signal Transmission Efficiency in Semiconductor Interconnect and Proposal of Enhanced Structures, MICROMACHINES, vol.15 No.10, 2024박종경
◾ Innovative Programming Approaches to Address Z-Interference in High-Density 3D NAND Flash Memory, ELECTRONICS, vol.13 No.16, 2024박종경
◾ Analyzing the Influence of Source/Drain Growth Height and Lateral Growth Depth in FinFETs Through XGBoost and SHAP, IEEE ELECTRON DEVICE LETTERS, vol.45 No.10 pp.1714~1716, 2024박종경
◾ 저온 Cu 하이브리드 본딩을 위한 폴리머 본딩, 마이크로전자및패키징학회지, 2024박종경
◾ Systematic Analysis of Spacer and Gate Length Scaling on Memory Characteristics in 3D NAND Flash Memory, APPLIED SCIENCES-BASEL, vol.14 No.15, 2024박종경
◾ First Demonstration of Enhanced Cu-Cu Bonding at Low Temperature With Ruthenium Passivation Layer, IEEE ACCESS, vol.12 pp.82396~82401, 2024박종경
◾ A Self-aligned Process for Simultaneous Fabrication of Short Channel and Spacer in Semiconductor Devices, JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, vol.24 No.3, 2024박종경
◾ Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory, ELECTRONICS, vol.13 No.6, 2024박종경
◾ Facilitating 3D Multi-Chip Integration through Low-Temperature Polymer-to-Polymer Bonding, Acs Applied Electronic Materials, 2024박종경
◾ A New 3-Dimensional Vertical Transistor with Channel Length Determination Using Dielectric Thickness, ELECTRONICS, 2024박종경
◾ Phase-shift controller for analog device application using 2-D material, CARBON LETTERS, vol.34 No.6 pp.1667~1672, 2024박종경
◾ Unraveling diffusion behavior in Cu-to-Cu direct bonding with metal passivation layers, SCIENTIFIC REPORTS, vol.14 No.1, 2024박종경
◾ 저온 Cu 하이브리드 본딩을 위한 SiCN의 본딩 특성 리뷰, 마이크로전자 및 패키징학회지, vol.30 No.4 pp.8~16, 2023박종경
◾ Guidelines for Area Ratio between Metal Lines and Vias to Improve the Reliability of Interconnect Systems in High-Density Electronic Devices, ELECTRONICS, vol.12 No.21, 2023박종경
◾ A Review of Cell Operation Algorithm for 3D NAND Flash Memory, APPLIED SCIENCES-BASEL, vol.12 No.21, 2022박종경
학술대회
- Jong Kyung Park, Seung-Yoon Kim, Ki-Hong Lee, Seung Ho Pyi, Seok-Hee Lee, and Byung Jin Cho, "Surface-controlled Ultrathin (2 nm) Poly-Si Channel Junctionless FET towards 3D NAND Flash Memory Applications", Symposium on VLSI Technology, Hawaii, USA, June 9-13, 2014
- 박종경, 이석희, 이기홍, 피승호, 조병진, "플래쉬 메모리 소자에서의 초기 VT 불안정 현상 개선에 관한 연구", 20th Korean Conference on Semiconductors, Hoengsung,
Korea, Feb 4-6, 2013
- 송승민, 박종경, 설원제, 조병진, "그래핀의 work-function 변이에 관한 연구", 20th
Korean Conference on Semiconductors, Hoengsung, Korea, Feb 4-6, 2013.
- Jong Kyung Park, Seok-Hee Lee, Ki-Hong Lee, Seung Ho Pyi, and Byung Jin Cho, " Dramatic Increase of Dielectric Constant of Al2O3 by Very Light Doping of La and Thermal Treatment and Its Application to Flash Memory Device ", 19th Korean Conference on Semiconductors, Seoul, Korea, Feb. 2012
- BJ Cho, SM Song, and JK Park, "Issues on Metal Contact and Gate Electrode of Graphene Based FET", The 4th International Conference on Recent Progress in Graphene Research (RPGR) 2012, p. 26, Beijing, China, Oct. 3-6, 2012 (Invited)
- Jong Kyung Park, Dong-Il Moon, Yang-Kyu Choi, Seok-Hee Lee, Ki-Hong Lee, Seung Ho Pyi, and Byung Jin Cho, "Origin of transient Vth shift after erase and its impact on 2D/3D structure charge trap Flash memory cell operations", International Electron Devices Meeting, San Francisco, CA, USA, Dec. 10-12, 2012
- Jong Kyung Park, Seung Min Song, Jeong Hun Mun, and Byung Jin Cho, "Dramatic Improvement of high-K Gate Dielectric Reliability by Replacing Metal Gate Electrode with Mono-Layer Graphene", Symposium on VLSI Technology, Hawaii, USA, Jun. 12-15, 2012
- Jong Kyung Park, Seung Min Song, Jeong Hun Mun, and Byung Jin Cho, "Graphene Gate Electrode for Advanced Silicon-Based CMOS Devices", Graphene Week 2012, Delft, Netherlands, Jun. 4-8, 2012
- 송승민, 박종경, 조병진, "금속/그래핀/산화막/반도체 구조에서 그래핀이 커패시턴스에 미치는 영향", 2011 Korean Carbon Society Spring Meeting, Seoul, Korea, May 19-20. 2011
- Jong Kyung Park, Youngmin Park, Seok-Hee Lee, Sung Kyu Lim, Jae Sub Oh, Moon Sig Joo, Kwon Hong, and Byung Jin Cho, "Enhancement of High temperature Data Retention by La2O3-Doped Nitride for Charge-Trap Type Flash Memory Device", 18th Korean Conference on Semiconductors, Jeju, Korea, Feb. 2011
- Jong Kyung Park, Youngmin Park, Sung Kyu Lim, Jae Sub Oh, Moon Sig Joo, Kwon Hong, and Byung Jin Cho, “In-Depth Study on Mechanism of the Performance Improvement by High Temperature Annealing of the Al2O3 in a Charge-Trap Type Flash Memory Device", International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 22-24, 2010
◾ Seon Woo Kim, Jong Kyung Park, The Advanced DC Circuit Model for Hybrid bonding in Dual Damascene Structures, The 19th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2024), Nangang District, Taipei City 11568, Taiwan, 2024박종경
◾ Jihun Kim, Jongkyung Park, Optimizing Low-Temperature Polymer Thermo Compression Bonding and Polymer Patterning for 3D Multi-Chip Integration, The 19th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2024), Nangang District, Taipei City 11568, Taiwan, 2024박종경
◾ Yeonju Kim, Jongkyung Park, Characterization and Optimization of SiCN films for Low-Temperature Cu Hybrid Bonding, The 19th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2024), Nangang District, Taipei City 11568, Taiwan, 2024박종경
◾ Min Seong Jeong, Jongkyung Park, Research on the Crystallinity of Metal Passivation Layer for Improving Low-Temperature Copper Bonding Performance, The 19th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2024), Nangang District, Taipei City 11568, Taiwan, 2024박종경
◾ Kyoungmin Shin, Jongkyung Park, Influence of Current Distribution Variations on Contact Resistance Measurement in Cu-Cu Bonding Interface, The 19th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT 2024), Nangang District, Taipei City 11568, Taiwan, 2024박종경
◾ Hee young Bae, Jong Kyung Park, 3D NAND 플래시 메모리의 ON Pitch Scaling에 따른 프로그램 속도 저하 분석, 한국반도체학술대회 포스터세션, 경주화백컨벤션센터, 2024박종경
◾ Hyeon Seo Yun, Jong Kyung Park, 3D NAND 메모리의 신뢰성 향상: Z 간섭 감소를 위한 새로운 프로그래밍 방식, 한국반도체학술대회 포스터세션, 경주화백컨벤션센터, 2024박종경
◾ Jihun Kim, Sang Woo Park, Min Seong Jung, Yeon Ju Kim, Jong Kyung Park, 3D멀티 칩 적층공정을 위한 폴리머-다이렉트릭 하이브리드 본딩, 한국반도체학술대회 포스터세션, 경주화백컨벤션센터, 2024박종경
◾ Min Seong Jeong, Sang Woo Park, Yeon Ju Kim, Ji Hoon Kim, Jong Kyung Park, 저온 구리 접합 성능 향상을 위한 금속 패시베이션 결정성에 관한 연구, 한국반도체학술대회 포스터세션, 경주화백컨벤션센터, 2024박종경
◾ Ye Eun Kim, Jong Kyung Park, 3D NAND 플래시 메모리의 제한된 질화물 트랩층 구조에 기반한 Z 간섭 조사, 한국반도체학술대회 포스터세션, 경주화백컨벤션센터, 2024박종경
◾ Sang Woo Park, Min Seong Jeong, Jong Kyung Park, Advancements in Metal Passivation Process for Low-Temperature Cu-Cu Direct Bonding, ISOCC 2023 프로시딩, Ramada Plaza Jeju Hotel, 2023박종경
◾ Yeon Ju Kim, Sang Woo Park, Min Seong Jeong, Jong Kyung Park, 저온 구리 하이브리드 본딩을 위한 확산 거동 및 칩 레벨 본딩 이해, 마이크로전자 및 패키징 학회지, Paradise Hotel Busan, 2023박종경
◾ Yeon Ju Kim, Sang Woo Park, Min Seong Jeong, Jong Kyung Park, Low Temperature Cu-Cu Direct Bonding with Ruthenium Passivation Layer, 마이크로전자 및 패키징 학회지, Paradise Hotel Busan, 2023박종경
◾ Yeon Ju Kim, Sang Woo Park, Min Seong Jeong, Jong Kyung Park, The Impact of CMP Process on Cu-SiO2 Hybrid Bonding, 마이크로전자 및 패키징 학회지, Paradise Hotel Busan, 2023박종경
◾ Ji hoon Kim, Yeon Ju Kim, Sang Woo Park, Min Seong Jeong, Jong Kyung Park, 3D 멀티칩 적층 공정을 위한 고분자-유전체 하이브리드 본딩, 마이크로전자 및 패키징 학회지, Paradise Hotel Busan, 2023박종경
◾ 김예은, 박종경, 3D NAND에서 confined nitride trap layer 구조에 따른 Z - interference 특성, 대한전자공학회 2023년도 하계종합학술대회, 제주호텔 제주(중문), 2023박종경
◾ 황진경, 박종경, 비대칭 프로그램 패스전압을 이용한 삼차원 낸드플래시의 Z-간섭 개선, 대한전자공학회 2023년도 하계종합학술대회, 롯데호텔 제주(중문), 2023박종경
◾ 정민성, 박종경, 저온 구리 하이브리드 본딩을 위한 금속 확산거동의 원인 고찰, 마이크로전자 및 패키징 학회지, 수원컨벤션센터 4F (광교중앙역, 경기도 수원시 영통구 광교중앙로 140), 2023박종경
◾ 박상우, 박종경, 저온 구리 하이브리드 본딩을 위한 금속 패시베이션 박막의 결정립 크기에 관한 고찰, 마이크로전자 및 패키징 학회지, 수원컨벤션센터 4F (광교중앙역, 경기도 수원시 영통구 광교중앙로 140), 2023박종경
저역서
- NONVOLATILE MEMORIES-Materials, Devices and Applications (Chapter 9 “Application of a High-k Dielectric for a Flash-Memory Device”), Jong Kyung Park, Tseung-Yuen Tseng, Simon M. Sze, and Byung Jin Cho, AMERICAN SCIENTIFIC PUBLISHERS, 2012
특허
- Semiconductor memory device and method of operating the same. US patent, 11328766, 2022.
- Memory device capable of improving a threshold voltage distribution of memory cells and method of operating the memory device. US patent, 11217317, 2022.
- Semiconductor device and operating method of a semiconductor device. US patent, 10930331, 2021.
- 메모리 장치 및 이의 동작 방법(Memory device and method of operating the same), 1020190091216, 2019
- 반도체 장치 및 반도체 장치의 동작 방법(SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE), 1020190068167, 2019
- 반도체 메모리 장치 및 그 동작 방법(SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF), 1020190140458, 2019
- 반도체 메모리 장치 및 이의 동작 방법(SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF), 1020160037530, 2016
- NON-VOLATILE MEMORY DEVICE AND MOSFET USING GRAPHENE GATE ELECTRODE, US patent, 13,342,282, 2012
- 반도체 장치의 박막 형성 방법(METHOD FOR FABRICATING THIN FILM IN SEMICONDUCTOR DEVICE), 1020110068442, 2011
- 비휘발성 메모리 소자 및 그 제조 방법(NON-VILATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME), 1020100013637, 2010
연구프로젝트
- Study on Characteristics of Interface between Polysilicon Channel and Tunnel Oxide in 3D Flash Memory Device, SK Hynix, 2013 – 2014
- Study on Juntionless Charge Trap Device for 3D NAND Flash Memory, SK Hynix, 2012-2013
- Device Operation Modeling for Retention Improvement of CTF Flash Memory, SK Hynix, 2011-2012
- Improvement of Data Retention of Flash Memory Using ALD charge trap layer, SK Hynix, 2010-2011
- Development of composite element implementation technology for organic and inorganic nanomaterials, Ministry of Education, Science and Engineering, 2009-2014
- Development of high-K dielectric process for Flash memory, SK Hynix, 2008-2010
기타(학회활동 등)
<활동>
- Advisory Professor, Samsung Electronics Future Technology Committee
- Editorial Director, The Korean Microelectronics and Packaging Society (KMEPS)
<수상>
- Annual Research Performance Excellence Award, KAIST, 2013
- Top 10 New Breakthrough Technology, KAIST, 2011
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